A field effect transistor (FET) (which is essential to the operation of some semiconductor devices such as a complementary metal oxide semiconductor (CMOS) transistor), includes a gate electrode, a source and a drain.
FIG. 1 is a flow chart illustrating a conventional method for forming a CMOS transistor. First, a device isolation layer is formed in predetermined regions of a semiconductor substrate to define an active region and a field region (block S1). The device isolation layer, (usually referred to as a field oxide layer), is typically formed by performing a local oxidation of silicon (LOCOS) method or a shallow trench isolation (STI) method.
Next, well regions are formed in the semiconductor substrate where the CMOS transistors will be formed (block S2). Specifically, an N well region is formed in a PMOS transistor region of the semiconductor substrate and a P well region is formed in an NMOS transistor region of the semiconductor substrate.
Subsequently, gate electrodes are formed on the well regions by forming a gate oxide layer and a polysilicon layer, and then etching them while using a gate mask pattern (block S3).
Next, a screen oxide layer is formed on an upper surface of the gate electrode, on the semiconductor substrate and on the sidewalls of the gate electrode by performing a re-oxidization process (block S4). The screen oxide layer cures or compensates for degradation of the gate oxide layer of the gate electrodes, which results from the etching process for forming the gate electrodes represented by block S3. Moreover, the screen oxide layer serves to protect the semiconductor substrate when an ion implantation process for forming a lightly doped drain (LDD) region is subsequently performed.
Next, LDD region is formed by performing the ion implantation process to avoid hot carrier creation due to the peak electric field in a drain edge of, for example, the NMOS transistor (block S5). The LDD region is formed so that its edges are aligned with the edges of the gate electrode.
Next, spacers are formed on the sidewalls of the gate electrodes (block S6). The spacers have a conventional structure consisting of a spacer nitride layer, a buffer oxide layer and a sealing nitride layer (N/O/N structure).
Subsequently, source/drain regions are formed in alignment with the edges of the spacers and expanded from the LDD regions by an ion implantation process (block S7).
Next, a silicide layer is formed on the source/drain regions in order to reduce the contact resistance thereof (block S8). This completes the fabrication of the CMOS transistor.
However, because the re-oxidation process for forming the screen oxide layer is performed at a high temperature for a long time, the well region and a channel region below the gate electrodes, (which have been formed before the re-oxidization process), are affected by the re-oxidation process, thereby degrading characteristics of the transistor such as the threshold voltage.
Like parts appearing in FIGS. 3A to 3F are represented by like reference characters.